Digi NS9215 Uživatelský manuál

NS9215 Hardware Reference 90000847_C Release date: 10 April 2008

10 Hardware Reference NS9215High speed bus system...138High-speed bus arbiters...

WORKING WITH THE CPUR9: Cache Lockdown register100 Hardware Reference NS9215Lockdown cache: Specific loading of addresses into a cache-wayUse this pro

. . . . .WORKING WITH THE CPUR10:TLB Lockdown registerwww.digiembedded.com 1018 Write <CRm>==0 to Cache Lockdown register (R9), setting L==1 for

WORKING WITH THE CPUR11 and R12 registers102 Hardware Reference NS9215Programming instructionsUse these instructions to program the TLB Lockdown regis

. . . . .WORKING WITH THE CPUR13:Process ID registerwww.digiembedded.com 103Use the Process ID register to determine the process that is currently run

WORKING WITH THE CPUR14 register104 Hardware Reference NS9215A1, A2, and A3 are the three instructions following the fast context switch.Context ID re

. . . . .WORKING WITH THE CPUDSPwww.digiembedded.com 105 Software emulation within the ARM-optimized JVM, which addresses the remaining 20% of the Ja

WORKING WITH THE CPUMemoryManagement Unit (MMU)106 Hardware Reference NS9215 Invalidate entire TLB using R8: TLB Operations register (see “R8:TLB Ope

. . . . .WORKING WITH THE CPUMemoryManagement Unit (MMU)www.digiembedded.com 107MMU program accessible registersThis table shows the CP15 registers th

WORKING WITH THE CPUMemoryManagement Unit (MMU)108 Hardware Reference NS9215The MMU table-walking hardware adds entries to the TLB. The translation in

. . . . .WORKING WITH THE CPUMemoryManagement Unit (MMU)www.digiembedded.com 109Table walk processFirst-level fetch Bits [31:14] of the TTB register a

. . . . .www.digiembedded.com 11AHB Error Detect Status 2 ... 160AHB Error Monitoring C

WORKING WITH THE CPUMemoryManagement Unit (MMU)110 Hardware Reference NS9215First-level fetch concatenation and addressThis address selects a 4-byte t

. . . . .WORKING WITH THE CPUMemoryManagement Unit (MMU)www.digiembedded.com 111First-level descriptor bit assignments: Priority encoding of fault sta

WORKING WITH THE CPUMemoryManagement Unit (MMU)112 Hardware Reference NS9215Section descriptor bit descriptionCoarse page table descriptorA coarse pag

. . . . .WORKING WITH THE CPUMemoryManagement Unit (MMU)www.digiembedded.com 113page tables have 1024 entries, splitting the 1 MB that the table descr

WORKING WITH THE CPUMemoryManagement Unit (MMU)114 Hardware Reference NS9215Second-level descriptorThe base address of the page table to be used is de

. . . . .WORKING WITH THE CPUMemoryManagement Unit (MMU)www.digiembedded.com 115 A tiny page descriptor provides the base address of a 1 KB block of

WORKING WITH THE CPUMemoryManagement Unit (MMU)116 Hardware Reference NS9215Translation sequence for large page referencesBecause the upper four bits

. . . . .WORKING WITH THE CPUMemoryManagement Unit (MMU)www.digiembedded.com 117Translating sequence for small page referencesIf a small page descript

WORKING WITH THE CPUMemoryManagement Unit (MMU)118 Hardware Reference NS9215Translation sequence for tiny page referencesPage translation involves one

. . . . .WORKING WITH THE CPUMMU faults and CPU abortswww.digiembedded.com 119When you use subpage permissions and the page entry has to be invalidate

12 Hardware Reference NS9215Low-power SDRAM partial array refresh ...204Memory map...

WORKING WITH THE CPUMMU faults and CPU aborts120 Hardware Reference NS9215register. If an access violation simultaneously generates more than one sour

. . . . .WORKING WITH THE CPUDomain access controlwww.digiembedded.com 121Compatibility issues To enable code to be ported easily to future architect

WORKING WITH THE CPUFault checking sequence122 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .WORKING WITH THE CPUFault checking sequencewww.digiembedded.com 123The conditions that generate each of the faults are discussed in the follo

WORKING WITH THE CPUFault checking sequence124 Hardware Reference NS9215Note:If an access generates an alignment fault, the access sequence aborts wit

. . . . .WORKING WITH THE CPUExternal abortswww.digiembedded.com 125interpreted in the same way as for a section (see “Interpreting access permission

WORKING WITH THE CPUTLB structure126 Hardware Reference NS9215Care must be taken if the translated address differs from the untranslated address, beca

. . . . .WORKING WITH THE CPUCaches and write bufferwww.digiembedded.com 127about the structure, replacement algorithm, or persistence of entries in t

WORKING WITH THE CPUCaches and write buffer128 Hardware Reference NS9215 The caches use pseudo-random or round-robin replacement, selected by the RR

. . . . .WORKING WITH THE CPUCaches and write bufferwww.digiembedded.com 129ICache I and M bit settingsThis table gives the I and M bit settings for t

. . . . .www.digiembedded.com 13222Memory banks constructed from 16-or 32-bit memory devices... 223Dynamic memory controller...

WORKING WITH THE CPUCache MVA and Set/Way formats130 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .WORKING WITH THE CPUCache MVA and Set/Way formatswww.digiembedded.com 131Generic, virtually indexed, virtually addressed cache001234567nTAG12

WORKING WITH THE CPUCache MVA and Set/Way formats132 Hardware Reference NS9215ARM926EJ-S cache formatARM926EJ-S cache associativityThe following point

. . . . .WORKING WITH THE CPUNoncachable instruction fetcheswww.digiembedded.com 133In this figure:A = log2 associativityFor example, with a 4-way cac

WORKING WITH THE CPUNoncachable instruction fetches134 Hardware Reference NS9215AHB behavior If instruction prefetching is disabled, all instruction f

. . . . .WORKING WITH THE CPUNoncachable instruction fetcheswww.digiembedded.com 135recommended that either a nonbuffered store (STR) or a noncached l

WORKING WITH THE CPUNoncachable instruction fetches136 Hardware Reference NS9215

137System Control ModuleCHAPTER 4The System Control Module configures and oversees system operations for the processor, and defines both the AMBA High

SYSTEM CONTROL MODULESystem bus arbiter138 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULESystem bus arbiterwww.digiembedded.com 1392 The arbiter stops evaluating the BRR until a bus grant is issued for the pre

14 Hardware Reference NS9215Static Memory Write Delay 0–3 registers...257StaticMemory Turn Round Delay

SYSTEM CONTROL MODULESystem bus arbiter140 Hardware Reference NS9215 If the bus is granted to a default master and continues to be in the IDLE state

. . . . .SYSTEM CONTROL MODULEAddress decodingwww.digiembedded.com 141BRC1[23:16] = 8’b1_0_00_0000 channel disabledBRC1[15:8] = 8’b1_0_00_0000 channel

SYSTEM CONTROL MODULEProgrammable timers142 Hardware Reference NS9215This table shows the hmaster[3:0] assignments for the processor.. . . . . . . . .

. . . . .SYSTEM CONTROL MODULEGeneral purpose timers/counterswww.digiembedded.com 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSTEM CONTROL MODULEBasic PWM function144 Hardware Reference NS9215 Interrupt enable Concatenate to up-stream timer/counter; that is, use up-stream

. . . . .SYSTEM CONTROL MODULEEnhanced PWM functionwww.digiembedded.com 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSTEM CONTROL MODULEHow the quadrature decoder/counter works146 Hardware Reference NS9215A quadrature decoder/counter module performs these tasks at

. . . . .SYSTEM CONTROL MODULEHow the quadrature decoder/counter workswww.digiembedded.com 147Monitors how far the encoder has movedThe counter keeps

SYSTEM CONTROL MODULEInterrupt controller148 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULEInterrupt controllerwww.digiembedded.com 149IRQ characteristics The IRQ interrupts are enabled by the respective enabli

. . . . .www.digiembedded.com 15Writing to other registers... 276Ethernet Control and Status

SYSTEM CONTROL MODULEInterrupt controller150 Hardware Reference NS9215The interrupt sources are assigned as shown:Interrupt ID Interrupt source0 Watch

. . . . .SYSTEM CONTROL MODULEVectored interrupt controller (VIC) flowwww.digiembedded.com 151. . . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSTEM CONTROL MODULEBootstrap initialization152 Hardware Reference NS9215PLL configuration and control system block diagram. . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULEBootstrap initializationwww.digiembedded.com 153Pin name Configuration bitsgpio_a[3] Endian configuration0 Little endian

SYSTEM CONTROL MODULESystem configuration registers154 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULESystem configuration registerswww.digiembedded.com 155A090 0074 Timer 9 Read and Capture registerA090 0078 Timer 6 High

SYSTEM CONTROL MODULESystem configuration registers156 Hardware Reference NS9215A090 00F8 Interrupt Vector Address Register Level 13A090 00FC Interrup

. . . . .SYSTEM CONTROL MODULESystem configuration registerswww.digiembedded.com 157A090 017C Clock Configuration registerA090 0180 Module Reset regis

SYSTEM CONTROL MODULEGeneral Arbiter Control register158 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULEAHB Error Detect Status 1www.digiembedded.com 159Channel allocation This is how the channels are assigned in the four re

16 Hardware Reference NS9215Transmit statistics counters address map ...307Transmit byte counter (A060 06E0)...

SYSTEM CONTROL MODULEAHB Error Detect Status 2160 Hardware Reference NS9215The AHB Error Detect Status 1 register records the haddr[31:0] value presen

. . . . .SYSTEM CONTROL MODULEAHB Error Monitoring Configuration registerwww.digiembedded.com 161Register bit assignment. . . . . . . . . . . . . . .

SYSTEM CONTROL MODULETimer Master Control register162 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULETimer Master Control registerwww.digiembedded.com 163Register bit assignmentBits Access Mnemonic Reset DescriptionD31:22

SYSTEM CONTROL MODULETimer 0–4 Control registers164 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULETimer 0–4 Control registerswww.digiembedded.com 165RegisterRegister bit assignment131211109876543215 1431 29 28 27 26 25

SYSTEM CONTROL MODULETimer 5 Control register166 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULETimer 5 Control registerwww.digiembedded.com 167Register bit assignmentBits Access Mnemonic Reset DescriptionD31:19 N/A

SYSTEM CONTROL MODULETimer 6–9 Control registers168 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULETimer 6–9 Control registerswww.digiembedded.com 169RegisterRegister bit assignment13121110987654321015 1431 29 28 27 26

. . . . .www.digiembedded.com 17Multicast Low Address Filter Register #6... 328Multicast Low Address Filter Reg

SYSTEM CONTROL MODULETimer 6–9 High registers170 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULETimer 6–9 Low registerswww.digiembedded.com 171RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . . .

SYSTEM CONTROL MODULETimer 6–9 High and Low Step registers172 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULETimer 0-9 Reload Count and Compare registerwww.digiembedded.com 173RegisterRegister bit assignment. . . . . . . . . . .

SYSTEM CONTROL MODULETimer 0-9 Read and Capture register174 Hardware Reference NS9215Register bit assignment. . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULEInterrupt Vector Address Register Level 31–0www.digiembedded.com 175. . . . . . . . . . . . . . . . . . . . . . . . . .

SYSTEM CONTROL MODULEISADDR register176 Hardware Reference NS9215Register bit assignmentThis is how the bits are assigned in each register, using data

. . . . .SYSTEM CONTROL MODULEInterrupt Status Activewww.digiembedded.com 177RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . . .

SYSTEM CONTROL MODULEInterrupt Status Raw178 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULESoftware Watchdog Timerwww.digiembedded.com 179Register bit assignment. . . . . . . . . . . . . . . . . . . . . . . . .

18 Hardware Reference NS9215Buffer length ...340Destination address [pointer].

SYSTEM CONTROL MODULEClock Configuration register180 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULEClock Configuration registerwww.digiembedded.com 181Register bit assignmentBits Access Mnemonic Reset DescriptionD31:29

SYSTEM CONTROL MODULEModule Reset register182 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULEModule Reset registerwww.digiembedded.com 183The Module Reset register resets each module on the AHB bus.RegisterRegiste

SYSTEM CONTROL MODULEMiscellaneous System Configuration and Status register184 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULEMiscellaneous System Configuration and Status registerwww.digiembedded.com 185Register bit assignmentBits Access Mnemoni

SYSTEM CONTROL MODULEPLL Configuration register186 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULEActive Interrupt Level ID Status registerwww.digiembedded.com 187. . . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSTEM CONTROL MODULEPower Management188 Hardware Reference NS9215Register bit assignmentBits Access Mnemonic Reset DescriptionD31 R/W Slp en 0x0 Depr

. . . . .SYSTEM CONTROL MODULEPower Managementwww.digiembedded.com 189D20 R/W WakeIntClr 0x0 CPU wake interrupt clearWrite a 1, followed by a 0 to cle

. . . . .www.digiembedded.com 19Last (L) bit ... 358Full (F) bit...

SYSTEM CONTROL MODULEAHB Bus Activity Status190 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULESystem Memory Chip Select 1 Dynamic Memory Base and Mask registerswww.digiembedded.com 191These control registers set th

SYSTEM CONTROL MODULESystem Memory Chip Select 2 Dynamic Memory Base and Mask registers192 Hardware Reference NS9215RegistersRegister bit assignmentSy

. . . . .SYSTEM CONTROL MODULESystem Memory Chip Select 3 Dynamic Memory Base and Mask registerswww.digiembedded.com 193RegistersRegister bit assignme

SYSTEM CONTROL MODULESystem Memory Chip Select 0 Static Memory Base and Mask registers194 Hardware Reference NS9215RegistersRegister bit assignmentSys

. . . . .SYSTEM CONTROL MODULESystem Memory Chip Select 1 Static Memory Base and Mask registerswww.digiembedded.com 195RegistersRegister bit assignmen

SYSTEM CONTROL MODULESystem Memory Chip Select 2 Static Memory Base and Mask registers196 Hardware Reference NS9215RegistersRegister bit assignmentSys

. . . . .SYSTEM CONTROL MODULESystem Memory Chip Select 3 Static Memory Base and Mask registerswww.digiembedded.com 197RegistersRegister bit assignmen

SYSTEM CONTROL MODULEGen ID register198 Hardware Reference NS9215RegistersRegister bit assignment. . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULEExternal Interrupt 0–3 Control registerwww.digiembedded.com 199RegisterRegister bit assignment. . . . . . . . . . . . .

©2008 Digi International Inc.Printed in the United States of America. All rights reserved.Digi, Digi International, the Digi logo, a Digi Internationa

20 Hardware Reference NS9215[Module] DMA RX Control...375[Module] DMA RX Buffer Descr

SYSTEM CONTROL MODULERTC Module Control register200 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SYSTEM CONTROL MODULERTC Module Control registerwww.digiembedded.com 201D03 R Rdy int 0x0 RTC clock ready interrupt status0 RTC clock ready i

SYSTEM CONTROL MODULERTC Module Control register202 Hardware Reference NS9215

203Memory ControllerCHAPTER 5The Multiport Memory Controller is an AMBA-compliant system-on-chip (SoC) peripheral that connects to the Advanced High-p

MEMORY CONTROLLERLow-power operation204 Hardware Reference NS9215 Power-saving modes that dynamically control SDRAM clk_en. Dynamic memory self-refr

. . . . .MEMORY CONTROLLERMemory mapwww.digiembedded.com 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY CONTROLLERMemory map206 Hardware Reference NS92152 When the power-on reset (reset_n) goes inactive, the processor starts booting from 0x0000000

. . . . .MEMORY CONTROLLERStatic memory controllerwww.digiembedded.com 2072 When the power-on reset (reset_n) goes inactive, the processor starts boot

MEMORY CONTROLLERStatic memory controller208 Hardware Reference NS9215Notes: Buffering enables the transaction order to be rearranged to improve memo

. . . . .MEMORY CONTROLLERStatic memory initializationwww.digiembedded.com 209time critical services, such as interrupt latency and low latency device

. . . . .www.digiembedded.com 21UART FIFO Control register... 409UART Line Control regis

MEMORY CONTROLLERStatic memory read control210 Hardware Reference NS9215 “Static Memory Extended Wait register” on page 247 (StaticExtendedWait)The n

. . . . .MEMORY CONTROLLERStatic memory read: Timing and parameterswww.digiembedded.com 211. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY CONTROLLERStatic memory read: Timing and parameters212 Hardware Reference NS9215External memory read transfer with two output enable delay stat

. . . . .MEMORY CONTROLLERStatic memory read: Timing and parameterswww.digiembedded.com 213Burst of zero wait states with fixed lengthThis diagram sho

MEMORY CONTROLLERAsynchronous page mode read214 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERAsynchronous page mode read: Timing and parameterswww.digiembedded.com 215External memory 32-bit burst read from 8-bit memor

MEMORY CONTROLLERStatic memory write control216 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERStatic memory Write: Timing and parameterswww.digiembedded.com 217External memory write transfer with two wait statesThis di

MEMORY CONTROLLERStatic memory Write: Timing and parameters218 Hardware Reference NS9215Two external memory write transfers with zero wait statesThis

. . . . .MEMORY CONTROLLERBus turnaroundwww.digiembedded.com 219. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22 Hardware Reference NS9215SPI module structure...434SPI controller...

MEMORY CONTROLLERBus turnaround: Timing and parameters220 Hardware Reference NS9215Write followed by a read with no turnaroundThis diagram shows a zer

. . . . .MEMORY CONTROLLERByte lane controlwww.digiembedded.com 221. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY CONTROLLERAddress connectivity222 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERAddress connectivitywww.digiembedded.com 223Memory banks constructed from 16-or 32-bit memory devicesFor memory banks constr

MEMORY CONTROLLERAddress connectivity224 Hardware Reference NS9215datat[31:0]data[31:0]data[31:16]data[15:0]data[31:24]data[23:16]data[15:8]data[7:0]Q

. . . . .MEMORY CONTROLLERDynamic memory controllerwww.digiembedded.com 225. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY CONTROLLERSDRAM Initialization226 Hardware Reference NS921510 Set the SDRAMInit value in the Dynamic Control register to 01 — Issue SDRAM Mode

. . . . .MEMORY CONTROLLERSDRAM Initializationwww.digiembedded.com 227Left-shift value table: 32-bit wide data bus SDRAM (BRC)Left-shift value table:

MEMORY CONTROLLERSDRAM address and data bus interconnect228 Hardware Reference NS9215Left-shift value table: 16-bit wide data bus SDRAM (BRC). . . . .

. . . . .MEMORY CONTROLLERSDRAM address and data bus interconnectwww.digiembedded.com 22932-bit wide configurationaddr[14] A12* A12 A12addr[15]addr[16

. . . . .www.digiembedded.com 23Register bit assignment ... 451Master Address register...

MEMORY CONTROLLERRegisters230 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERRegisterswww.digiembedded.com 231A070 0044 DynamictWR Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL)A070 0048 Dy

MEMORY CONTROLLERControl register232 Hardware Reference NS9215Reset values Reset values will be noted in the description column of each register table

. . . . .MEMORY CONTROLLERControl registerwww.digiembedded.com 233Register bit assignmentBits Access Mnemonic DescriptionD31:03 N/A Reserved N/A (do n

MEMORY CONTROLLERStatus register234 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERDynamic Memory Control registerwww.digiembedded.com 235RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . .

MEMORY CONTROLLERDynamic Memory Refresh Timer register236 Hardware Reference NS9215Register bit assignment. . . . . . . . . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERDynamic Memory Read Configuration registerwww.digiembedded.com 237The Dynamic Memory Refresh Timer register configures dynam

MEMORY CONTROLLERDynamic Memory Precharge Command Period register238 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERDynamic Memory Active to Precharge Command Period registerwww.digiembedded.com 239Register bit assignmentDynamic Memory Acti

24 Hardware Reference NS9215ADC Configuration register...475ADC Clock Configuration reg

MEMORY CONTROLLERDynamic Memory Self-refresh Exit Time register240 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERDynamic Memory Data-in to Active Command Time registerwww.digiembedded.com 241RegisterRegister bit assignment. . . . . . . .

MEMORY CONTROLLERDynamic Memory Write Recovery Time register242 Hardware Reference NS9215Register bit assignment. . . . . . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERDynamic Memory Active to Active Command Period registerwww.digiembedded.com 243. . . . . . . . . . . . . . . . . . . . . . .

MEMORY CONTROLLERDynamic Memory Exit Self-refresh register244 Hardware Reference NS9215Note:The Dynamic Memory Auto Refresh Period register is used fo

. . . . .MEMORY CONTROLLERDynamic Memory Active Bank A to Active Bank B Time registerwww.digiembedded.com 245RegisterRegister bit assignmentDynamic Me

MEMORY CONTROLLERDynamic Memory Load Mode register to Active Command Time register246 Hardware Reference NS9215Register bit assignmentDynamic Memory L

. . . . .MEMORY CONTROLLERStatic Memory Extended Wait registerwww.digiembedded.com 247. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEMORY CONTROLLERDynamic Memory Configuration 0–3 registers248 Hardware Reference NS9215Use the Dynamic Memory Configuration 0–3 registers to program

. . . . .MEMORY CONTROLLERDynamic Memory Configuration 0–3 registerswww.digiembedded.com 249Address mapping for the Dynamic Memory Configuration regis

. . . . .www.digiembedded.com 25Clock timing ... 511System PLL referenc

MEMORY CONTROLLERDynamic Memory RAS and CAS Delay 0–3 registers250 Hardware Reference NS9215Chip select and memory devicesA chip select can be connect

. . . . .MEMORY CONTROLLERStaticMemory Configuration 0–3 registerswww.digiembedded.com 251The Dynamic Memory RAS and CAS Delay 0–3 registers allow you

MEMORY CONTROLLERStaticMemory Configuration 0–3 registers252 Hardware Reference NS9215RegisterRegister bit assignment13121110987654321015 1431 29 28 2

. . . . .MEMORY CONTROLLERStaticMemory Configuration 0–3 registerswww.digiembedded.com 253D07 R/W PB Byte lane state0 For reads, all bits in byte_lane

MEMORY CONTROLLERStaticMemory Write Enable Delay 0–3 registers254 Hardware Reference NS9215Note:Synchronous burst mode memory devices are not supporte

. . . . .MEMORY CONTROLLERStatic Memory Output Enable Delay 0–3 registerswww.digiembedded.com 255Register bit assignment. . . . . . . . . . . . . . .

MEMORY CONTROLLERStatic Memory Read Delay 0–3 registers256 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERStatic Memory Write Delay 0–3 registerswww.digiembedded.com 257modified during system initialization, or when there are no c

MEMORY CONTROLLERStaticMemory Turn Round Delay 0–3 registers258 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . .

. . . . .MEMORY CONTROLLERStaticMemory Turn Round Delay 0–3 registerswww.digiembedded.com 259Register bit assignmentTo prevent bus contention on the e

26 Hardware Reference NS9215

MEMORY CONTROLLERStaticMemory Turn Round Delay 0–3 registers260 Hardware Reference NS9215

. . . . .ETHERNET COMMUNICATION MODULEwww.digiembedded.com 261Ethernet Communication ModuleCHAPTER 6The Ethernet Communication module consists of an E

ETHERNET COMMUNICATION MODULEEthernet MAC262 Hardware Reference NS9215Ethernet communications module. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEEthernet MACwww.digiembedded.com 263MAC module block diagramMAC module featuresFeature DescriptionMAC Core 10/10

ETHERNET COMMUNICATION MODULEStation address logic (SAL)264 Hardware Reference NS9215PHY interface mappings This table shows how the different PHY int

. . . . .ETHERNET COMMUNICATION MODULEStatistics modulewww.digiembedded.com 265module. The filtering options, listed next, are programmed in the Stati

ETHERNET COMMUNICATION MODULEEthernet front-end module266 Hardware Reference NS9215The counters support a clear on read capability that is enabled whe

. . . . .ETHERNET COMMUNICATION MODULEReceive packet processorwww.digiembedded.com 267The 2K byte RX_FIFO allows the entire Ethernet frame to be buffe

ETHERNET COMMUNICATION MODULEReceive packet processor268 Hardware Reference NS9215Transferring a frame to system memoryThe RX_RD logic manages the tra

. . . . .ETHERNET COMMUNICATION MODULETransmit packet processorwww.digiembedded.com 269Receive buffer descriptor field definitions. . . . . . . . . .

27Pinout (265)CHAPTER 1The NS9215 offers a connection to a 10/100 Ethernet network, as well as a glueless connection to SDRAM, PC100 DIMM, flash, EEPR

ETHERNET COMMUNICATION MODULETransmit packet processor270 Hardware Reference NS9215reside in different buffers in system memory, several buffer descri

. . . . .ETHERNET COMMUNICATION MODULETransmit packet processorwww.digiembedded.com 271Transmitting a frameSetting the EXTDMA (enable transmit DMA) bi

ETHERNET COMMUNICATION MODULETransmit packet processor272 Hardware Reference NS9215The TX_WR logic examines the status received from the MAC after it

. . . . .ETHERNET COMMUNICATION MODULEEthernet slave interfacewww.digiembedded.com 273– A packet consisting of multiple, linked buffer descriptors doe

ETHERNET COMMUNICATION MODULEResets274 Hardware Reference NS9215Status bits The status bits for all interrupts are available in the Ethernet Interrupt

. . . . .ETHERNET COMMUNICATION MODULEMulticast address filteringwww.digiembedded.com 275. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEClock synchronization276 Hardware Reference NS9215Multicast address filtering example 2To accept multicast packets with d

. . . . .ETHERNET COMMUNICATION MODULEEthernet Control and Status registerswww.digiembedded.com 277. . . . . . . . . . . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEEthernet Control and Status registers278 Hardware Reference NS9215A060 0A0C RXDPTR RX_D Buffer Descriptor Pointer registe

. . . . .ETHERNET COMMUNICATION MODULEEthernet General Control Register #1www.digiembedded.com 279. . . . . . . . . . . . . . . . . . . . . . . . . .

PINOUT (265)Memory bus interface28 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEEthernet General Control Register #1280 Hardware Reference NS9215Register bit assignmentBits Access Mnemonic Reset Descri

. . . . .ETHERNET COMMUNICATION MODULEEthernet General Control Register #1www.digiembedded.com 281D22 R/W ETXDMA 0 Enable transmit DMA0 Disable transm

ETHERNET COMMUNICATION MODULEEthernet General Control Register #2282 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEEthernet General Status registerwww.digiembedded.com 283Register bit assignment. . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEEthernet Transmit Status register284 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEEthernet Transmit Status registerwww.digiembedded.com 285Register bit assignmentBits Access Mnemonic Reset Desc

ETHERNET COMMUNICATION MODULEEthernet Receive Status register286 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEEthernet Receive Status registerwww.digiembedded.com 287RegisterRegister bit assignment13 12 11 10 9 8 7 6 5 4 3

ETHERNET COMMUNICATION MODULEMAC Configuration Register #1288 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEMAC Configuration Register #2www.digiembedded.com 289. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .PINOUT (265)Memory bus interfacewww.digiembedded.com 29M1 addr[0] U I/O 4 Address bus, PLL NR[0]L1 data[31] U I/O 4 Data busK2 data[30] U I/O

ETHERNET COMMUNICATION MODULEMAC Configuration Register #2290 Hardware Reference NS9215D09 R/W LONGP 0 Long preamble enforcement0 Allows any length pr

. . . . .ETHERNET COMMUNICATION MODULEBack-to-Back Inter-Packet-Gap registerwww.digiembedded.com 291PAD operation table for transmit frames. . . . . .

ETHERNET COMMUNICATION MODULENon Back-to-Back Inter-Packet-Gap register292 Hardware Reference NS9215Register bit assignment. . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULECollision Window/Retry registerwww.digiembedded.com 293Register bit assignment. . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEMaximum Frame register294 Hardware Reference NS9215Register bit assignment. . . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEMII Management Configuration registerwww.digiembedded.com 295Register bit assignment. . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEMII Management Command register296 Hardware Reference NS9215Clocks field settings. . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEMII Management Address registerwww.digiembedded.com 297RegisterRegister bit assignmentNote:If both SCAN and READ

ETHERNET COMMUNICATION MODULEMII Management Write Data register298 Hardware Reference NS9215Register bit assignment. . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEMII Management Indicators registerwww.digiembedded.com 299RegisterRegister bit assignment. . . . . . . . . . . .

PINOUT (265)Ethernet interface MAC30 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEStation Address registers300 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEStation Address Filter registerwww.digiembedded.com 301Register bit assignments for all three registersNote:Octe

ETHERNET COMMUNICATION MODULERegisterHash Tables302 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEStatistics registerswww.digiembedded.com 303HT2 Address: A060 0508Register bit assignment. . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEStatistics registers304 Hardware Reference NS9215Receive statistics counters address mapReceive byte counter (A060 069C)I

. . . . .ETHERNET COMMUNICATION MODULEStatistics registerswww.digiembedded.com 305Receive FCS error counter (A060 06A4)Incremented for each frame rece

ETHERNET COMMUNICATION MODULEStatistics registers306 Hardware Reference NS9215Receive alignment error counter (A060 06BC)Incremented for each received

. . . . .ETHERNET COMMUNICATION MODULEStatistics registerswww.digiembedded.com 307Receive jabber counter (A060 06D8)Incremented for frames received th

ETHERNET COMMUNICATION MODULEStatistics registers308 Hardware Reference NS9215Transmit packet counter (A060 06E4)Incremented for each transmitted pack

. . . . .ETHERNET COMMUNICATION MODULEStatistics registerswww.digiembedded.com 309Transmit multiple collision packet counter (A060 0700)Incremented fo

. . . . .PINOUT (265)General purpose I/O (GPIO)www.digiembedded.com 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEStatistics registers310 Hardware Reference NS9215Transmit oversize frame counter (A060 0724)Incremented for each transmit

. . . . .ETHERNET COMMUNICATION MODULEStatistics registerswww.digiembedded.com 311RegisterRegister bit assignmentCarry Register 2 Address: A060 0734C1

ETHERNET COMMUNICATION MODULEStatistics registers312 Hardware Reference NS9215RegisterRegister bit assignmentCarry Register 1 Mask registerAddress: A0

. . . . .ETHERNET COMMUNICATION MODULEStatistics registerswww.digiembedded.com 313RegisterRegister bit assignmentM1RMCM1RBCM1RXPM1RXCM1RXUM1RALNotused

ETHERNET COMMUNICATION MODULEStatistics registers314 Hardware Reference NS9215Carry Register 2 Mask registerAddress: A060 073CRegisterRegister bit ass

. . . . .ETHERNET COMMUNICATION MODULERX_A Buffer Descriptor Pointer registerwww.digiembedded.com 315. . . . . . . . . . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULERX_C Buffer Descriptor Pointer register316 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEEthernet Interrupt Status registerwww.digiembedded.com 317. . . . . . . . . . . . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEEthernet Interrupt Status register318 Hardware Reference NS9215D21 R/C RXDONEB 0 Assigned to RX interrupt.Complete receiv

. . . . .ETHERNET COMMUNICATION MODULEEthernet Interrupt Enable registerwww.digiembedded.com 319. . . . . . . . . . . . . . . . . . . . . . . . . . .

PINOUT (265)General purpose I/O (GPIO)32 Hardware Reference NS9215Note:All GPIOs except 12 and 16 to 31 are reset to mode 3, input. GPIO 12 is reset t

ETHERNET COMMUNICATION MODULETX Buffer Descriptor Pointer register320 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULETransmit Recover Buffer Descriptor Pointer registerwww.digiembedded.com 321. . . . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULETX Stall Buffer Descriptor Pointer register322 Hardware Reference NS9215Register bit assignment. . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULERX_A Buffer Descriptor Pointer Offset registerwww.digiembedded.com 323Register bit assignment. . . . . . . . . .

ETHERNET COMMUNICATION MODULERX_B Buffer Descriptor Pointer Offset register324 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULERX_D Buffer Descriptor Pointer Offset registerwww.digiembedded.com 325Register bit assignment. . . . . . . . . .

ETHERNET COMMUNICATION MODULERX Free Buffer register326 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULEMulticast Address Filter registerswww.digiembedded.com 327. . . . . . . . . . . . . . . . . . . . . . . . . . .

ETHERNET COMMUNICATION MODULEMulticast Address Filter registers328 Hardware Reference NS9215Multicast Low Address Filter Register #6Address: A060 0A58

. . . . .ETHERNET COMMUNICATION MODULEMulticast Address Mask registerswww.digiembedded.com 329Multicast High Address Filter Register #6Address: A060 0

. . . . .PINOUT (265)General purpose I/O (GPIO)www.digiembedded.com 33G17 gpio[8] U I/O 2 0 DCD / TXC UART C1 Ext DMA Done Ch 12 Ext Timer Event Out C

ETHERNET COMMUNICATION MODULEMulticast Address Mask registers330 Hardware Reference NS9215Multicast Low Address Mask Register #4Address: A060 0A90 Mul

. . . . .ETHERNET COMMUNICATION MODULEMulticast Address Filter Enable registerwww.digiembedded.com 331Multicast High Address Mask Register #5Address:

ETHERNET COMMUNICATION MODULETX Buffer Descriptor RAM332 Hardware Reference NS9215Register bit assignment. . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULERX FIFO RAMwww.digiembedded.com 333Offset+4Offset+8Offset+CSee “Transmit buffer descriptor format” on page 270,

ETHERNET COMMUNICATION MODULESample hash table code334 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .ETHERNET COMMUNICATION MODULESample hash table codewww.digiembedded.com 335(*MERCURY_EFE).ht2.bits.data = SWAP32(hash_table[1]);(*MERCURY_EFE

ETHERNET COMMUNICATION MODULESample hash table code336 Hardware Reference NS9215/*** Function: void set_hash_bit (BYTE *table, int bit)** Description:

. . . . .ETHERNET COMMUNICATION MODULESample hash table codewww.digiembedded.com 337** Return Values:** bit position to set in hash table**/#define PO

ETHERNET COMMUNICATION MODULESample hash table code338 Hardware Reference NS9215bp = rotate (bp, RIGHT, 1);}}// CRC calculation done. The 6-bit result

. . . . .EXTERNAL DMADMA transferswww.digiembedded.com 339External DMACHAPTER 6The external DMA interface provides two external channels for external

PINOUT (265)General purpose I/O (GPIO)34 Hardware Reference NS9215D3 gpio[16] U I/O 4 0 data[0]1 DCD UART B2 Ext Int Ch 0 (dup)3 gpio[16]B2 gpio[17] U

EXTERNAL DMADMA buffer descriptor340 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .EXTERNAL DMADescriptor list processingwww.digiembedded.com 341Note:Optimal performance is achieved when the destination address is aligned on

EXTERNAL DMAPeripheral DMA read access342 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .EXTERNAL DMAPeripheral DMA write accesswww.digiembedded.com 343Peripheral DMA single read accessPeripheral DMA burst read access. . . . . . .

EXTERNAL DMAPeripheral REQ and DONE signaling344 Hardware Reference NS9215Determining the width of PDEN Use the memory controller’s Static Memory Writ

. . . . .EXTERNAL DMAStatic RAM chip select configurationwww.digiembedded.com 345DONE signal  The external peripheral can terminate the DMA transfer

EXTERNAL DMAControl and Status registers346 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .EXTERNAL DMADMA Control registerwww.digiembedded.com 347RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . . . . . . . . .

EXTERNAL DMADMA Control register348 Hardware Reference NS9215Register bit assignmentBit(s) Access Mnemonic Reset DescriptionD31 R/W CE 0 Channel enabl

. . . . .EXTERNAL DMADMA Control registerwww.digiembedded.com 349D22:21 R/W DB 0 Destination burstDefines the AHB maximum burst size allowed when writ

. . . . .PINOUT (265)General purpose I/O (GPIO)www.digiembedded.com 35F4 gpio[26] U I/O 4 0 data[10]1DSR UART D2 PIC_1_GEN_IO[0](I/O)3 gpio[26]F3 gpio

EXTERNAL DMADMA Status and Interrupt Enable register350 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .EXTERNAL DMADMA Status and Interrupt Enable registerwww.digiembedded.com 351Register bit assignmentBit(s) Access Mnemonic Reset DescriptionD3

EXTERNAL DMADMA Peripheral Chip Select register352 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .EXTERNAL DMADMA Peripheral Chip Select registerwww.digiembedded.com 353Register bit assignmentBit(s) Access Mnemonic Reset DefinitionD31:02 R

EXTERNAL DMADMA Peripheral Chip Select register354 Hardware Reference NS9215

. . . . .AES DATA ENCRYPTION/DECRYPTION MODULEwww.digiembedded.com 355AES Data Encryption/Decryption ModuleCHAPTER 6The AES data encryption/decryption

AES DATA ENCRYPTION/DECRYPTION MODULEAES DMA buffer descriptor356 Hardware Reference NS9215Block diagramData blocks The AES module works on 128-bit bl

. . . . .AES DATA ENCRYPTION/DECRYPTION MODULEAES DMA buffer descriptorwww.digiembedded.com 357AES buffer descriptor diagramField definitions follow.S

AES DATA ENCRYPTION/DECRYPTION MODULEAES DMA buffer descriptor358 Hardware Reference NS9215AES op code Indicates the contents of the data buffer assoc

. . . . .AES DATA ENCRYPTION/DECRYPTION MODULEDecryptionwww.digiembedded.com 359The DMA channel does not try a transfer when the F bit is clear. The D

PINOUT (265)General purpose I/O (GPIO)36 Hardware Reference NS9215D17 gpio[36] U I/O 2 0 Ethernet MII RX DV1 PIC_0_GEN_IO[4](I/O)(dup)2 Reserved3 gpio

AES DATA ENCRYPTION/DECRYPTION MODULECBC, CFB, OFB, and CTR processing360 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .AES DATA ENCRYPTION/DECRYPTION MODULECCM modewww.digiembedded.com 361 For encryption, software must set up this buffer descriptor sequence:

AES DATA ENCRYPTION/DECRYPTION MODULECCM mode362 Hardware Reference NS9215

363I/O Hub ModuleCHAPTER 9The I/O hub provides access to the low speed ports on the processor through one master port on the AHB bus. The low speed po

I/O HUB MODULEDMA controller364 Hardware Reference NS9215 31 March 2008Block diagramAHB slave interfaceThe CPU has access to the control and status re

. . . . .I/O HUB MODULEDMA controllerwww.digiembedded.com 365Buffer descriptors The peripheral buffer data is held in buffers in external memory, link

I/O HUB MODULEDMA controller366 Hardware Reference NS9215 31 March 2008 For transmit channels. CPU sets the F bit after the data is written to a buff

. . . . .I/O HUB MODULETransmit DMA examplewww.digiembedded.com 367HDLCSPINot applicable.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O HUB MODULEControl and status register address maps368 Hardware Reference NS9215 31 March 20082 Verifies that the data buffer is valid by making su

. . . . .I/O HUB MODULEControl and status register address mapswww.digiembedded.com 369Note:Registers 9000_0000 – 9000_7FFF and registers 9000_8000 –

. . . . .PINOUT (265)General purpose I/O (GPIO)www.digiembedded.com 37D12 gpio[46] U I/O 2 0 Ethernet MII TXD[2]1 PIC_1_GEN_IO[6](I/O)(dup)2 Reserved3

I/O HUB MODULEControl and status register address maps370 Hardware Reference NS9215 31 March 2008UART C register address mapUART D register address ma

. . . . .I/O HUB MODULEControl and status register address mapswww.digiembedded.com 371SPI register address mapAD register address mapReserved Registe

I/O HUB MODULE[Module] Interrupt and FIFO Status register372 Hardware Reference NS9215 31 March 2008RTC register address mapIO Hardware Assist registe

. . . . .I/O HUB MODULE[Module] Interrupt and FIFO Status registerwww.digiembedded.com 373RegisterRegister bit assignment13121110987654321015 1431 29

I/O HUB MODULE[Module] Interrupt and FIFO Status register374 Hardware Reference NS9215 31 March 2008D26 R/W* RXFOFIP 0x0 RX FIFO overflow interrupt pe

. . . . .I/O HUB MODULE[Module] DMA RX Controlwww.digiembedded.com 375. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O HUB MODULE[Module] DMA RX Buffer Descriptor Pointer376 Hardware Reference NS9215 31 March 2008RegisterRegister bit assignment. . . . . . . . . . .

. . . . .I/O HUB MODULE[Module] RX Interrupt Configuration registerwww.digiembedded.com 377RegisterRegister bit assignment. . . . . . . . . . . . . .

I/O HUB MODULE[Module] Direct Mode RX Status FIFO378 Hardware Reference NS9215 31 March 2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .I/O HUB MODULE[Module] Direct Mode RX Data FIFOwww.digiembedded.com 379Register bit assignment. . . . . . . . . . . . . . . . . . . . . . . .

PINOUT (265)General purpose I/O (GPIO)38 Hardware Reference NS9215J4 gpio[56] U I/O 2 0 RTS/RS485 Control UART B (dup)1 PIC_0_BUS_1[13](I/O)2 PIC_1_BU

I/O HUB MODULE[Module] DMA TX Control380 Hardware Reference NS9215 31 March 2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .I/O HUB MODULE[Module] DMA TX Buffer Descriptor Pointerwww.digiembedded.com 381. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O HUB MODULE[Module] Direct Mode TX Data FIFO382 Hardware Reference NS9215 31 March 2008Register bit assignment. . . . . . . . . . . . . . . . . . .

. . . . .I/O HUB MODULE[Module] Direct Mode TX Data Last FIFOwww.digiembedded.com 383Register bit assignment. . . . . . . . . . . . . . . . . . . . .

I/O HUB MODULE[Module] Direct Mode TX Data Last FIFO384 Hardware Reference NS9215 31 March 2008

. . . . .SERIAL CONTROL MODULE: UARTwww.digiembedded.com 385Serial Control Module: UART CHAPTER 10The processor ASIC supports four independent univers

SERIAL CONTROL MODULE: UARTNormal mode operation386 Hardware Reference NS9215UART module structure. . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: UARTBaud rate generatorwww.digiembedded.com 387. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: UARTHardware-based flow control388 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: UARTARM wakeup on character recognitionwww.digiembedded.com 389character completes, regardless of any flow control mec

. . . . .PINOUT (265)General purpose I/O (GPIO)www.digiembedded.com 39N8 gpio[66] U I/O 2 0 TXD UART D (dup)1 PIC_0_BUS_1[23](I/O)2 PIC_1_BUS_1[23](I/

SERIAL CONTROL MODULE: UARTWrapper Control and Status registers390 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: UARTWrapper Configuration registerwww.digiembedded.com 391. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: UARTWrapper Configuration register392 Hardware Reference NS9215D17 R/W RXFLUSH 0 Resets the contents of the 64-byte RXFIFO.Writ

. . . . .SERIAL CONTROL MODULE: UARTInterrupt Enable registerwww.digiembedded.com 393. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: UARTInterrupt Enable register394 Hardware Reference NS9215D19 R/W OFLOW 0 Enable overflow errorEnables interrupt generation if

. . . . .SERIAL CONTROL MODULE: UARTInterrupt Status registerwww.digiembedded.com 395. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: UARTInterrupt Status register396 Hardware Reference NS9215RegisterRegister bit assignment13121110987654321015 1431 29 28 27 26

. . . . .SERIAL CONTROL MODULE: UARTInterrupt Status registerwww.digiembedded.com 397D11 R/W1TC MATCH3 0 Character match3Indicates that a receive char

SERIAL CONTROL MODULE: UARTReceive Character GAP Control register398 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: UARTReceive Buffer GAP Control registerwww.digiembedded.com 399. . . . . . . . . . . . . . . . . . . . . . . . . . . .

PINOUT (265)General purpose I/O (GPIO)40 Hardware Reference NS9215T15 gpio[76] U I/O 2 0 PIC_0_CTL_IO[0](I/O)1 PIC_1_CTL_IO[0](I/O)2 Ext Timer Event i

SERIAL CONTROL MODULE: UARTReceive Character-Based Flow Control register400 Hardware Reference NS9215The Receive Character Match Control registers con

. . . . .SERIAL CONTROL MODULE: UARTReceive Character-Based Flow Control registerwww.digiembedded.com 401Caution:Be aware that if multiple matches occ

SERIAL CONTROL MODULE: UARTForce Transmit Character Control register402 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: UARTARM Wakeup Control registerwww.digiembedded.com 403RegisterRegister bit assignment. . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: UARTTransmit Byte Count404 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: UARTUART Receive Bufferwww.digiembedded.com 405. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: UARTUART Baud Rate Divisor LSB406 Hardware Reference NS9215Register bit assignment. . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: UARTUART Interrupt Enable registerwww.digiembedded.com 407RegisterRegister bit assignment. . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: UARTUART Interrupt Identification register408 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: UARTUART FIFO Control registerwww.digiembedded.com 409. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .PINOUT (265)General purpose I/O (GPIO)www.digiembedded.com 41K13 gpio[86] U I/O 2 0 PIC_0_BUS_0[6](I/O)1 PIC_1_BUS_0[6](I/O)2 Ext Timer Event

SERIAL CONTROL MODULE: UARTUART Line Control register410 Hardware Reference NS9215RegisterRegister bit assignment13121110987654321015 1431 29 28 27 26

. . . . .SERIAL CONTROL MODULE: UARTUART Modem Control registerwww.digiembedded.com 411. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: UARTUART Modem Status register412 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: UARTUART Modem Status registerwww.digiembedded.com 413RegisterRegister bit assignment13121110987654321015 1431 29 28 2

SERIAL CONTROL MODULE: UARTUART Modem Status register414 Hardware Reference NS9215

. . . . .SERIAL CONTROL MODULE: HDLCReceive and transmit operationswww.digiembedded.com 415Serial Control Module: HDLC CHAPTER 11The HDLC module allow

SERIAL CONTROL MODULE: HDLCClocking416 Hardware Reference NS9215Receive operation In the receiver, each byte is marked with status to indicate end-of-

. . . . .SERIAL CONTROL MODULE: HDLCData encodingwww.digiembedded.com 417between the opening and closing flags, except for the inserted zeroes, to the

SERIAL CONTROL MODULE: HDLCDigital phase-locked-loop (DPLL) operation: Encoding418 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: HDLCDPLL operation: Adjustment ranges and output clockswww.digiembedded.com 419DPLL-tracked bit cell boundariesThe DPL

PINOUT (265)General purpose I/O (GPIO)42 Hardware Reference NS9215C16 gpio[96] U I/O 2 0 PIC_0_BUS_1[0](I/O)1 PIC_1_BUS_1[0](I/O)2 PIC_0_CAN_RXD(I)(du

SERIAL CONTROL MODULE: HDLCDPLL operation: Adjustment ranges and output clocks420 Hardware Reference NS9215NRZ and NRZI encodingWith NRZ and NRZI enco

. . . . .SERIAL CONTROL MODULE: HDLCNormal mode operationwww.digiembedded.com 421only uses the clock transitions to track the bit-cell boundaries, by

SERIAL CONTROL MODULE: HDLCWrapper and HDLC Control and Status registers422 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: HDLCWrapper Configuration registerwww.digiembedded.com 423RegisterRegister bit assignment13121110987654321015 1431 29

SERIAL CONTROL MODULE: HDLCInterrupt Enable register424 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: HDLCInterrupt Status registerwww.digiembedded.com 425. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: HDLCInterrupt Status register426 Hardware Reference NS9215RegisterRegister bit assignment13121110987654321015 1431 29 28 27 26

. . . . .SERIAL CONTROL MODULE: HDLCHDLC Data Register 1www.digiembedded.com 427. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: HDLCHDLC Data register 3428 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: HDLCHDLC Control Register 1www.digiembedded.com 429. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .PINOUT (265)System clockwww.digiembedded.com 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: HDLCHDLC Clock Divider Low430 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: HDLCHDLC Clock Divider Highwww.digiembedded.com 431Use the HDLC CLock Divider Low register to set bits 07:00 of the cl

SERIAL CONTROL MODULE: HDLCHDLC Clock Divider High432 Hardware Reference NS9215Register bit assignmentBits Access Mnemonic Reset DescriptionD31:08 R N

. . . . .SERIAL CONTROL MODULE: SPIwww.digiembedded.com 433Serial Control Module: SPI CHAPTER 12The processor ASIC contains a single high speed, four-

SERIAL CONTROL MODULE: SPISPI controller434 Hardware Reference NS9215SPI module structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: SPISPI clocking modeswww.digiembedded.com 435. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: SPISPI clock generation436 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: SPISystem boot-over-SPI operationwww.digiembedded.com 437Available strapping optionsEEPROM/FLASH headerThe boot-over-S

SERIAL CONTROL MODULE: SPISystem boot-over-SPI operation438 Hardware Reference NS9215Time to completionThe boot-over-SPI operation is performed in two

. . . . .SERIAL CONTROL MODULE: SPISPI Control and Status registerswww.digiembedded.com 439. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PINOUT (265)System clock44 Hardware Reference NS9215System clock drawing

SERIAL CONTROL MODULE: SPIClock Generation register440 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .SERIAL CONTROL MODULE: SPIInterrupt Enable registerwww.digiembedded.com 441Use this register to define the data rate of the interface.This re

SERIAL CONTROL MODULE: SPIInterrupt Status register442 Hardware Reference NS9215Use the Interrupt Enable register to enable interrupt generation on sp

. . . . .SERIAL CONTROL MODULE: SPISPI timing characteristicswww.digiembedded.com 443RegisterRegister bit assignment. . . . . . . . . . . . . . . . .

SERIAL CONTROL MODULE: SPISPI timing characteristics444 Hardware Reference NS9215Notes:1 The unit clock refers to the SPI master clock.2 The SPI maste

. . . . .SERIAL CONTROL MODULE: SPISPI timing characteristicswww.digiembedded.com 4452 The numbers shown here are for a 7.5 Mhz SPI slave interface cl

SERIAL CONTROL MODULE: SPISPI timing characteristics446 Hardware Reference NS9215

. . . . .I2C MASTER/SLAVE INTERFACEPhysical I2C buswww.digiembedded.com 447I2C Master/Slave InterfaceCHAPTER 13The I2C master/slave interface provides

I2C MASTER/SLAVE INTERFACEI2C external addresses448 Hardware Reference NS9215serial clock. Serial clock modulation can be controlled by both the trans

. . . . .I2C MASTER/SLAVE INTERFACEI2C command interfacewww.digiembedded.com 449. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .PINOUT (265)System modewww.digiembedded.com 45RTC clock and battery backup drawingNote: If RTC battery backup is not used, the following conn

I2C MASTER/SLAVE INTERFACEI2C registers450 Hardware Reference NS9215bus owner, the transaction goes through. If the module loses bus arbitration, an M

. . . . .I2C MASTER/SLAVE INTERFACEStatus Receive Data registerwww.digiembedded.com 451Register bit assignment. . . . . . . . . . . . . . . . . . . .

I2C MASTER/SLAVE INTERFACEMaster Address register452 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .I2C MASTER/SLAVE INTERFACESlave Address registerwww.digiembedded.com 453Register bit assignment. . . . . . . . . . . . . . . . . . . . . . .

I2C MASTER/SLAVE INTERFACEConfiguration register454 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .I2C MASTER/SLAVE INTERFACEInterrupt Codeswww.digiembedded.com 455. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2C MASTER/SLAVE INTERFACESoftware driver456 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .I2C MASTER/SLAVE INTERFACEFlow chartswww.digiembedded.com 457. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2C MASTER/SLAVE INTERFACEFlow charts458 Hardware Reference NS9215Slave module (normal mode, 16-bit)Note: STATUS_REG and RX_DATA_REG are read simultan

459Real Time Clock ModuleCHAPTER 14The Real Time Clock (RTC) module tracks the time of the day to an accuracy of 10 milliseconds and provides calendar

PINOUT (265)System mode46 Hardware Reference NS9215sys_mode_2 sys_mode_1 sys_mode_0 Description0 0 0 manufacturing test0 0 1 manufacturing test0 1 0 m

REAL TIME CLOCK MODULERTC configuration and status registers460 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .REAL TIME CLOCK MODULE12/24 Hour registerwww.digiembedded.com 461Register bit assignment. . . . . . . . . . . . . . . . . . . . . . . . . . .

REAL TIME CLOCK MODULETime register462 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .REAL TIME CLOCK MODULECalendar registerwww.digiembedded.com 463. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REAL TIME CLOCK MODULETime Alarm register464 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .REAL TIME CLOCK MODULECalendar Alarm registerwww.digiembedded.com 465. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REAL TIME CLOCK MODULEEvent Flags register466 Hardware Reference NS9215RegisterRegister bit assignment. . . . . . . . . . . . . . . . . . . . . . . .

. . . . .REAL TIME CLOCK MODULEEvent Flags registerwww.digiembedded.com 467RegisterRegister bit assignment13 12 11 10 9 8 7 6 5 4 3 2 1 015 1431 29 28

REAL TIME CLOCK MODULEInterrupt Enable register468 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .REAL TIME CLOCK MODULEInterrupt Disable registerwww.digiembedded.com 469. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .PINOUT (265)System resetwww.digiembedded.com 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REAL TIME CLOCK MODULEInterrupt Enable Status register470 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .REAL TIME CLOCK MODULEGeneral Status registerwww.digiembedded.com 471. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REAL TIME CLOCK MODULEGeneral Status register472 Hardware Reference NS9215

473Analog-to-Digital Converter (ADC) ModuleCHAPTER 15The NS9215 ASIC supports a 12-bit successive approximation analog-to-digital converter (ADC). To

ANALOG-TO-DIGITAL CONVERTER (ADC) MODULEADC DMA procedure474 Hardware Reference NS9215ADC control blockThe ADC control block provides access between t

. . . . .ANALOG-TO-DIGITAL CONVERTER (ADC) MODULEADC control and status registerswww.digiembedded.com 4752 Set up the ADC DMA control registers and bu

ANALOG-TO-DIGITAL CONVERTER (ADC) MODULEADC Configuration register476 Hardware Reference NS9215RegisterRegister bit assignment13121110987654321015 143

. . . . .ANALOG-TO-DIGITAL CONVERTER (ADC) MODULEADC Clock Configuration registerwww.digiembedded.com 477. . . . . . . . . . . . . . . . . . . . . . .

ANALOG-TO-DIGITAL CONVERTER (ADC) MODULEADC Output Registers 0-7478 Hardware Reference NS9215RegisterRegister bit assignment13121110987654321015 1431

. . . . .TIMINGElectrical characteristicswww.digiembedded.com 479TimingCHAPTER 16This chapter provides the electrical specifications, or timing, integ

PINOUT (265)JTAG Test48 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIMINGElectrical characteristics480 Hardware Reference NS9215Recommended operating conditionsRecommended operating conditions specify voltage and temp

. . . . .TIMINGDC electrical characteristicswww.digiembedded.com 481. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIMINGReset and edge sensitive input timing requirements482 Hardware Reference NS9215Ouputs All electrical outputs are 3.3V interface. DC electrical o

. . . . .TIMINGReset and edge sensitive input timing requirementswww.digiembedded.com 483If an external device driving the reset or edge sensitive inp

TIMINGMemory Timing484 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .TIMINGMemory Timingwww.digiembedded.com 485SDRAM burst read (16-bit)Notes:1 This is the bank and RAS address. 2 This is the CAS address.pr e

TIMINGMemory Timing486 Hardware Reference NS9215SDRAM burst read (16 bit), CAS latency = 3Notes:1 This is the bank and RAS address.2 This is the CAS a

. . . . .TIMINGMemory Timingwww.digiembedded.com 487SDRAM burst write (16 bit)Notes:1 This is the bank and RAS address.2 This is the CAS address.pr e

TIMINGMemory Timing488 Hardware Reference NS9215SDRAM burst read (32 bit)Notes:1 This is the bank and RAS address.2 This is the CAS address.prech g ac

. . . . .TIMINGMemory Timingwww.digiembedded.com 489SDRAM burst read (32 bit), CAS latency = 3Notes:1 This is the bank and RAS address.2 This is the C

. . . . .PINOUT (265)ADCwww.digiembedded.com 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIMINGMemory Timing490 Hardware Reference NS9215SDRAM burst write (32-bit)Notes:1 This is the bank and RAS address.2 This is the CAS address.prechg ac

. . . . .TIMINGMemory Timingwww.digiembedded.com 491SDRAM load modeM4M9M8M7M5SD L dM d tdop cod eclk_outdy_cs_n<3:0>* ras_ncas_nwe_naddr<11:0

TIMINGMemory Timing492 Hardware Reference NS9215SDRAM refresh modeM9M8M7M6M6M6M6clk_outdy_cs0_ndy_cs1_ndy_cs2_ndy_cs3_nras_ncas_nwe_n

. . . . .TIMINGMemory Timingwww.digiembedded.com 493Clock enable timingM1 3M14M3clk_enable.td clk_outclk_en<3:0>SDRAM cycle

TIMINGMemory Timing494 Hardware Reference NS9215Values in SRAM timing diagramsThe next table describes the values shown in the SRAM timing diagrams. N

. . . . .TIMINGMemory Timingwww.digiembedded.com 495static_rd_0wt.mifStatic RAM read cycles with 0 wait states WTRD = 1 WOEN = 0 If the PB field is

TIMINGMemory Timing496 Hardware Reference NS9215Static RAM asynchronous page mode read, WTPG = 1 WTPG = 1 WTRD = 2 If the PB field is set to 1, all

. . . . .TIMINGMemory Timingwww.digiembedded.com 497Static RAM read cycle with configurable wait states WTRD = from 1 to 15 WOEN = from 0 to 15 If

TIMINGMemory Timing498 Hardware Reference NS9215Static RAM sequential write cycles WTWR = 0 WWEN = 0 During a 32-bit transfer, all four byte_lane s

. . . . .TIMINGMemory Timingwww.digiembedded.com 499Static RAM write cycle WTWR = 0 WWEN = 0 During a 32-bit transfer, all four byte_lane signals w

5Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cha

PINOUT (265)POR and battery-backed logic50 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIMINGMemory Timing500 Hardware Reference NS9215Static write cycle with configurable wait states WTWR = from 0 to 15 WWEN = from 0 to 15 The WTWR f

. . . . .TIMINGMemory Timingwww.digiembedded.com 501Slow peripheral acknowledge timingThe table below describes the values shown in the slow periphera

TIMINGMemory Timing502 Hardware Reference NS9215Slow peripheral acknowledge readSlow peripheral acknowledge writeM32 M26M17 M18M19M20M31M27 M28M23 M24

. . . . .TIMINGMemory Timingwww.digiembedded.com 503Ethernet timing All AC characteristics are measured with 10pF, unless otherwise noted.The table be

TIMINGMemory Timing504 Hardware Reference NS9215I2C timing All AC characteristics are measured with 10pF, unless otherwise noted.The table below descr

. . . . .TIMINGMemory Timingwww.digiembedded.com 505SPI Timing All AC characteristics are measured with 10pF, unless otherwise noted.The next table de

TIMINGMemory Timing506 Hardware Reference NS9215Notes:1 Active level of SPI enable is inverted (that is, 1) if the CSPOL bit in Serial Channel Control

. . . . .TIMINGMemory Timingwww.digiembedded.com 507SPI master mode 0 and 1: 2-byte transferNote: SPI data can be reversed such that LSB is first. Use

TIMINGMemory Timing508 Hardware Reference NS9215SPI slave mode 0 and 1: 2-byte transferNote: SPI data can be reversed such that LSB is first. Use the

. . . . .TIMINGReset and hardware strapping timingwww.digiembedded.com 509. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .PINOUT (265)Power and groundwww.digiembedded.com 51If the RTC feature is not used, the inputs must be terminated as shown below.If the RTC fe

TIMINGJTAG timing510 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .TIMINGClock timingwww.digiembedded.com 511. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TIMINGClock timing512 Hardware Reference NS9215

513PackagingCHAPTER 17Below is the processor package, 265 LF-XBGA. Diagrams that follow show the processor dimensions: top, bottom, and side views. .

PACKAGINGProcessor Dimensions514 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .PACKAGINGProcessor Dimensionswww.digiembedded.com 515

PACKAGINGProcessor Dimensions516 Hardware Reference NS9215

517Change logCHAPTER 18The following changes were made since the last revision of this document.. . . . . . . . . . . . . . . . . . . . . . . . . . .

PINOUT (265)Power and ground52 Hardware Reference NS9215

53I/O Control ModuleCHAPTER 2The NS9215 ASIC contains 108 pins that are designated as general purpose I/O (GPIO).  The first 16 GPIO can be configure

I/O CONTROL MODULEControl and Status registers54 Hardware Reference NS9215A090_200C GPIO Configuration Register #3 R/W 0x18181810A090_2010 GPIO Config

. . . . .I/O CONTROL MODULEGPIO Configuration registerswww.digiembedded.com 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O CONTROL MODULEGPIO Configuration registers56 Hardware Reference NS9215GPIO Configuration Register #0Address: A090_2000GPIO Configuration Register

. . . . .I/O CONTROL MODULEGPIO Configuration registerswww.digiembedded.com 57GPIO Configuration Register #2Address: A090_2008GPIO Configuration Regis

I/O CONTROL MODULEGPIO Configuration registers58 Hardware Reference NS9215GPIO Configuration Register #4Address: A090_2010GPIO Configuration Register

. . . . .I/O CONTROL MODULEGPIO Configuration registerswww.digiembedded.com 59GPIO Configuration Register #6Address: A090_2018GPIO Configuration Regis

6 Hardware Reference NS9215GPIO Configuration Register #15 ...63GPIO Configuration Register #16 ...

I/O CONTROL MODULEGPIO Configuration registers60 Hardware Reference NS9215GPIO Configuration Register #8Address: A090_2020GPIO Configuration Register

. . . . .I/O CONTROL MODULEGPIO Configuration registerswww.digiembedded.com 61GPIO Configuration Register #10Address: A090_2028GPIO Configuration Regi

I/O CONTROL MODULEGPIO Configuration registers62 Hardware Reference NS9215GPIO Configuration Register #12Address: A090_2030GPIO Configuration Register

. . . . .I/O CONTROL MODULEGPIO Configuration registerswww.digiembedded.com 63GPIO Configuration Register #14Address: A090_2038GPIO Configuration Regi

I/O CONTROL MODULEGPIO Configuration registers64 Hardware Reference NS9215GPIO Configuration Register #16Address: A090_2040GPIO Configuration Register

. . . . .I/O CONTROL MODULEGPIO Configuration registerswww.digiembedded.com 65GPIO Configuration Register #18Address: A090_2048GPIO Configuration Regi

I/O CONTROL MODULEGPIO Configuration registers66 Hardware Reference NS9215GPIO Configuration Register #20Address: A090_2050GPIO Configuration Register

. . . . .I/O CONTROL MODULEGPIO Configuration registerswww.digiembedded.com 67GPIO Configuration Register #22Address: A090_2058GPIO Configuration Regi

I/O CONTROL MODULEGPIO Configuration registers68 Hardware Reference NS9215GPIO Configuration Register #24Address: A090_2060GPIO Configuration Register

. . . . .I/O CONTROL MODULEGPIO Configuration registerswww.digiembedded.com 69GPIO Configuration Register #26Address: A090_206813121110987654321015 14

. . . . .www.digiembedded.com 7ICache and DCache behavior ...90R2: Translation Table Base regis

I/O CONTROL MODULEGPIO Control registers70 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .I/O CONTROL MODULEGPIO Control registerswww.digiembedded.com 71GPIO Control Register #1Address: A090_2070D25 R/W GPIO25 0 GPIO[25] control bi

I/O CONTROL MODULEGPIO Control registers72 Hardware Reference NS9215GPIO Control Register #2Address: A090_2074D22 R/W GPIO54 0 GPIO[54] control bitD23

. . . . .I/O CONTROL MODULEGPIO Control registerswww.digiembedded.com 73GPIO Control Register #3Address: A090_2078D19 R/W GPIO83 0 GPIO[83] control bi

I/O CONTROL MODULEGPIO Status registers74 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .I/O CONTROL MODULEGPIO Status registerswww.digiembedded.com 75GPIO Status Register #2Address: A090_2084D26 R GPIO58 Undefined GPIO[58] status

I/O CONTROL MODULEMemory Bus Configuration register76 Hardware Reference NS9215GPIO Status Register #3Address: A090_2088. . . . . . . . . . . . . . .

. . . . .I/O CONTROL MODULEMemory Bus Configuration registerwww.digiembedded.com 77Bit(s) Access Mnemonic Reset DescriptionD02:00 R/W CS0 0x4 Controls

I/O CONTROL MODULEMemory Bus Configuration register78 Hardware Reference NS9215D14:12 R/W CS4 0x6 Controls which system memory chip select is routed t

. . . . .I/O CONTROL MODULEMemory Bus Configuration registerwww.digiembedded.com 79D25 R/W APUDIS 0x0 Address bus pullup control(Applicable only to ad

8 Hardware Reference NS9215Access instructions ...103Register format ...

I/O CONTROL MODULEMemory Bus Configuration register80 Hardware Reference NS9215

81Working with the CPUCHAPTER 3This processor core is based on the ARM926EJ-S processor. The ARM926EJ-S processor belongs to the ARM9 family of genera

WORKING WITH THE CPUInstruction sets82 Hardware Reference NS9215Arm926EJ-S process block diagramThis drawing shows the main blocks in the ARM926EJ-S p

. . . . .WORKING WITH THE CPUSystem control processor (CP15) registerswww.digiembedded.com 83Java instruction setIn Java state, the processor core exe

WORKING WITH THE CPUSystem control processor (CP15) registers84 Hardware Reference NS9215Figure 1: CP15 MRC and MCR bit patternThe mnemonics for these

. . . . .WORKING WITH THE CPUSystem control processor (CP15) registerswww.digiembedded.com 85Note:In all cases, reading from or writing any data value

WORKING WITH THE CPUR0: ID code and cache type status registers86 Hardware Reference NS9215 The B bit is set to 0 at reset if the BIGENDINIT signal i

. . . . .WORKING WITH THE CPUR0: ID code and cache type status registerswww.digiembedded.com 87You can access the cache type register by reading CP15

WORKING WITH THE CPUR1: Control register88 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .WORKING WITH THE CPUR1: Control registerwww.digiembedded.com 89Control register Bit functionality131 19 16 15 12 11 10 9 8 7 3 0218 17 14 13

. . . . .www.digiembedded.com 9MMU faults and CPU aborts... 119Alignment fault checking

WORKING WITH THE CPUR1: Control register90 Hardware Reference NS9215ICache and DCache behaviorThe M, C, I, and RR bits directly affect ICache and DCac

. . . . .WORKING WITH THE CPUR2: Translation Table Base registerwww.digiembedded.com 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

WORKING WITH THE CPUR4 register92 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .WORKING WITH THE CPUR6: Fault Address registerwww.digiembedded.com 93Status and domain fieldsThis table shows the encodings used for the stat

WORKING WITH THE CPUR7:Cache Operations register94 Hardware Reference NS9215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . .WORKING WITH THE CPUR7:Cache Operations registerwww.digiembedded.com 95Cache operation functionsThis table lists the cache operation function

WORKING WITH THE CPUR7:Cache Operations register96 Hardware Reference NS9215Modified virtual address format (MVA)This is the modified virtual address

. . . . .WORKING WITH THE CPUR8:TLB Operations registerwww.digiembedded.com 97Note:The test and clean DCache instruction MRC p15, 0, r15, c7, c10, 3 i

WORKING WITH THE CPUR9: Cache Lockdown register98 Hardware Reference NS9215 The invalidate TLB operations invalidate all the unpreserved entries in t

. . . . .WORKING WITH THE CPUR9: Cache Lockdown registerwww.digiembedded.com 99Instruction or data lockdown registerThe first four bits of this regist