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System boot
8
NS9750B-A1 Datasheet 03/2006
System boot
There are two ways to boot the NS9750B-A1 system:
From a fast Flash over the system memory bus
From an inexpensive, but slower, serial EEPROM through SPI port B
Both boot methods are glueless. The bootstrap pin,
RESET_DONEn, indicates where to boot on a
system powerup. Flash boot can be done from 8-bit, 16-bit, or 32-bit ROM or Flash.
Serial EEPROM boot is supported by NS9750B-A1 hardware. A configuration header in the EEPROM
specifies total number of words to be fetched from EEPROM, as well as a system memory
configuration and a memory controller configuration. The boot engine configures the memory
controller and system memory, fetches data from low-cost serial EEPROM, and writes the data to
external system memory, holding the CPU in reset, then enables the CPU.
Reset
Master reset using an external reset pin resets NS9750B-A1. Only the AHB bus error status registers
retain their values; software read resets these error status registers. The input reset pin can be
driven by a system reset circuit or a simple power-on reset circuit.
RESET_DONE as an input
Used at bootup only:
When set to 0, the system boots from SDRAM through the serial SPI EEPROM.
When set to 1, the system boots from Flash/ROM. This is the default.
RESET_DONE as an output
Sets to 1, per Step 6 in the boot sequence:
If the system is booting from serial EEPROM through the SPI port, the boot program must be loaded
into the SDRAM before the CPU is released from reset. The memory controller is powered up with
dy_cs_n[0] enabled with a default set of SDRAM configurations. The default address range for
dy_cs_n[0] is from 0x0000 0000. The other chip selects are disabled.
SPI boot sequence
1 When the system reset turns to inactive, the reset signal to the CPU is still held active.
2 An I/O module on the peripheral bus (BBus) reads from a serial ROM device that contains the
memory controller settings and the boot program.
3 The BBus-to-AHB bridge requests and gets the system bus.
- NS9750B-A1 Datasheet 1
- Contents 3
- NS9750B-A1 Datasheet 03/2006 4
- NS9750B-A1 Features 5
- 2 6
- System-level interfaces 8
- System configuration 9
- Table 2: PLL ND[4:0] 10
- Pin name Configuration bits 10
- General Purpose ID register 11
- System boot 12
- System Clock 13
- NS9750B-A1 14
- USB clock 15
- System Memory interface 16
- Pin # Signal Name 17
- I/O Description 17
- Name I/O Description 20
- Ethernet interface 22
- Clock generation/system pins 23
- PCI interface 24
- PCI/CardBus signals 26
- 24 28
- GPIO MUX 29
- Pin # Signal name 30
- Table 12: GPIO MUX pinout 30
- USB Power 35
- Controller 35
- CLSTN[0] 36
- MLSTN[0] 36
- CUSTN[0] 37
- RED[0] 38
- GREEN[0], BLUE[0] 38
- C interface 39
- USB Interface 39
- Reserved pins 41
- Address and register maps 42
- BBus peripheral address map 43
- Electrical characteristics 44
- Maximum power dissipation 45
- Typical power dissipation 45
- DC electrical characteristics 46
- USB DC electrical outputs 47
- 44 48
- Power sequencing 49
- Memory timing 50
- SDRAM burst read (16-bit) 51
- SDRAM burst write (16-bit) 52
- SDRAM burst read (32-bit) 52
- SDRAM burst write (32-bit) 53
- SDRAM load mode 54
- SDRAM refresh mode 54
- Clock enable timing 54
- SRAM timing 55
- 52 56
- WTWR = from 0 to 15 60
- 57 61
- 58 62
- Ethernet timing 63
- Ethernet MII timing 64
- Ethernet RMII timing 64
- PCI timing 65
- Internal PCI arbiter timing 66
- 64 68
- C timing 69
- LCD timing 70
- 68 72
- LCD output timing 73
- SPI timing 74
- 72 76
- IEEE 1284 timing 77
- USB timing 78
- USB full speed load 79
- USB low speed load 79
- 80
- JTAG timing 81
- Clock timing 82
- 79 83
- Packaging 84
- NS9750B-A1, 388 BGA 86
- Product specifications 87
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