Digi NS9750 Uživatelský manuál stáhnout pdf (Strana 23)

Clock generation/system pins

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Clock generation/system pins

Pin # Signal name

U/D

(mA)

I/O Description

C8 x1_sys_osc I System clock oscillator circuit input

D9 x1_usb_osc I USB clock crystal oscillator circuit input. (Connect

to GND if USB is not used.)

A7 x2_usb_osc O USB clock crystal oscillator circuit output

AC21 reset_done U 2 I/O CPU is enabled once the boot program is loaded.

Reset_done is set to 1.

H25 reset_n U I System reset input signal.

AD20 bist_en_n I Enable internal BIST operation

AF21 pll_test_n I Enable PLL testing

AE21 scan_en_n I Enable internal scan testing

B18 sys_pll_dvdd System clock PLL 1.5V digital power

A18 sys_pll_dvss System clock PLL digital ground

B17 sys_pll_avdd System clock PLL 3.3V analog power

C17 sys_pll_avss System clock PLL analog ground

J2 lcdclk U I External LCD clock input

D2 sreset_n I System reset. sreset_n is the same as reset, but

does not reset the system PLL.

E3 sreset_n_enable I

 Tie to 3.3V to enable the sreset_n input.

 Tie to ground to disable the sreset_n input.

T2 boot_strap[0] U 2 I/O Chip select 1 static memory byte_lane_enable_n,

or write_enable_n for byte-wide devices bootstrap

select

N3 boot_strap[1] U 2 I/O CardBus mode bootstrap select

P1 boot_strap[2] U 2 I/O Memory interface read mode bootstrap select

P2 boot_strap[3] U 2 I/O Chip select 1 data width bootstrap select

P3 boot_strap[4] U 2 I/O Chip select 1 data width bootstrap select

Table 8: Clock generation/system pins pinout

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 87 88

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Digi NS9750 Uživatelský manuál Strana 23