Digi NS9750 Uživatelský manuál stáhnout pdf (Strana 13)

System Clock

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4 The memory controller settings are read from the serial EEPROM and used to initialize the

memory controller.

5 The BBus-to-AHB bridge loads the boot program into the SDRAM, starting at address 0.

6 The reset signal going to the CPU is released once the boot program is loaded. RESET_DONE is

now set to 1.

7 The CPU begins to execute code from address 0x0000 0000.

You can use one of these software resets to reset the NS9750B-A1. Select the reset by setting the

appropriate bit in the appropriate register:

 Watchdog timer can issue reset upon Watchdog timer expiration.

 Software reset can reset individual internal modules or all modules except memory and CPU.

 The system is reset whenever software sets the PLL SW change bit to 1.

Hardware reset duration is 4ms for PLL to stabilize. Software reset duration depends on speed

grade, as shown in Table 3.

The minimum reset pulse width is 10 crystal clocks.

System Clock

The system clock reference is provided to the NS9750B-A1 by an external oscillator; Table 4 shows

sample clock frequency settings for each chip speed grade.

The oscillator must be connected to the

x1_sys_osc input (C8 pin) on the NS9750B-A1, as shown in

Figure 2.

Speed grade CPU clock cycles Duration

200 MHz 128 640 ns

162 MHz 128 790 ns

125 MHz 128 1024 ns

Table 3: Software reset duration

Speed cpu_clk hclk (main bus) bbus_clk

200 MHz 200 (199.0656) 99.5328 49.7664

162 MHz 162.2016 81.1008 40.5504

125 MHz 125.3376 62.6688 31.3344

Table 4: Sample clock frequency settings with 29.4912 MHz oscillator

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 87 88

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Digi NS9750 Uživatelský manuál Strana 13