Digi NS9750 Uživatelský manuál stáhnout pdf (Strana 55)

SRAM timing

www.digi.com

       51

SRAM timing

Table 27 describes the values shown in the SRAM timing diagrams.

Notes:

1 Only one of the four dy_cs_n signals is used. The diagrams show the active low configuration, which

can be reversed (active high) with the PC field. Use this formula to calculate the length of the st_cs_n

signal:

Tacc + board delay + (optional buffer delays, both address out and data in) + 10ns

Parameter Description Min Max Unit Notes

M15 clock high to data out valid +2 ns

M16 data out hold time from clock high -2 ns

M17 clock high to address valid +2 ns

M18 address hold time from clock high -2 ns

M19 clock high to st_cs_n low +2 ns 1

M20 clock high to st_cs_n high +2 ns 1

M21 clock high to we_n low +2 ns

M22 clock high to we_n high +2 ns

M23 clock high to byte_lanes low +2 ns

M24 clock high to byte_lanes high +2 ns

M25 data input setup time to rising clk 4.5 ns

M26 data input hold time to rising clk 4.5 ns

M27 clock high to oe_n low +2 ns

M28 clock high to oe_n high +2 ns

Table 27: SRAM timing parameters

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 87 88

Žádné komentáře

Digi NS9750 Uživatelský manuál Strana 55