Digi NS9750 Uživatelský manuál Strana 37
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Hodnocené. / 5. Na základě hodnocení zákazníků
LCD module signals
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Tabl e 1 5 s h ow s wh i ch CLD[23:0] pins provide the pixel data to the TFT panel for each of the
multiplexing modes of operation.
CLD[11]
AE6=LCD data bit 11 (O2)
AE8=LCD data bit 11 (O2)
N/A CLSTN[4] N/A
MLSTN[0]
1
N/A MLSTN[4]
CLD[10]
AD7=LCD data bit 10 (O2)
AD9=LCD data bit 10 (O2)
N/A CLSTN[5] N/A MLSTN[1] N/A MLSTN[5]
CLD[9]
AD8=LCD data bit 9 (O2)
AF8=LCD data bit 9 (O2)
N/A CLSTN[6] N/A MLSTN[2] N/A MLSTN[6]
CLD[8]
AF7=LCD data bit 8 (O2)
AE9=LCD data bit 8 (O2)
N/A CLSTN[7] N/A MLSTN[3] N/A MLSTN[7]
CLD[7]
AE8=LCD data bit 7 (O1)
CUSTN[0]
1
CUSTN[0]
1
N/A N/A MUSTN[0]
MUSTN[0]
1
CLD[6]
AD9=LCD data bit 6 (O1)
CUSTN[1] CUSTN[1] N/A N/A MUSTN[1] MUSTN[1]
CLD[5]
AF8=LCD data bit 5 (O1)
CUSTN[2] CUSTN[2] N/A N/A MUSTN[2] MUSTN[2]
CLD[4]
AE9=LCD data bit 4 (O1)
CUSTN[3] CUSTN[3] N/A N/A MUSTN[3] MUSTN[3]
CLD[3]
AF9=LCD data bit 3 (O1)
CUSTN[4] CUSTN[4] MUSTN[0]
MUSTN[0]
1
MUSTN[4] MUSTN[4]
CLD[2]
AD10=LCD data bit 2 (O1)
CUSTN[5] CUSTN[5] MUSTN[1] MUSTN[1] MUSTN[5] MUSTN[5]
CLD[1]
AE10=LCD data bit 1 (O1)
CUSTN[6] CUSTN[6] MUSTN[2] MUSTN[2] MUSTN[6] MUSTN[6]
CLD[0]
AF10=LCD data bit 0 (O1)
CUSTN[7] CUSTN[7] MUSTN[3] MUSTN[3] MUSTN[7] MUSTN[7]
1 This data bit corresponds to the first “pixel position.” For example, for an 8-bit mono STN display,
CUSTN[0] is the leftmost pixel on the panel and CUSTN[7] is the rightmost pixel within the 8-bit data.
For a color STN display, bits [7, 6, 5] form the leftmost pixel.
External pin TFT 24 bit TFT 15 bit
CLD[23] BLUE[7] Reserved
CLD[22] BLUE[6] Reserved
CLD[21] BLUE[5] Reserved
CLD[20] BLUE[4] Reserved
CLD[19] BLUE[3] Reserved
CLD[18] BLUE[2] Reserved
CLD[17] BLUE[1] BLUE[4]
CLD[16] BLUE[0] BLUE[3]
Table 15: CLD[23:0] pin descriptions for TFT display
Ext
pin
GPIO pin &
description
Color
STN
single
panel
Color
STN
dual
panel
4-bit
mono
STN
single
panel
4-bit
mono
STN
dual
panel
8-bit
mono
STN
single
panel
8-bit
mono
STN
dual
panel
Table 14: CLD[23:0] pin descriptions for STN display
- NS9750B-A1 Datasheet 1
- Contents 3
- NS9750B-A1 Datasheet 03/2006 4
- NS9750B-A1 Features 5
- 2 6
- System-level interfaces 8
- System configuration 9
- Table 2: PLL ND[4:0] 10
- Pin name Configuration bits 10
- General Purpose ID register 11
- System boot 12
- System Clock 13
- NS9750B-A1 14
- USB clock 15
- System Memory interface 16
- Pin # Signal Name 17
- I/O Description 17
- Name I/O Description 20
- Ethernet interface 22
- Clock generation/system pins 23
- PCI interface 24
- PCI/CardBus signals 26
- 24 28
- GPIO MUX 29
- Pin # Signal name 30
- Table 12: GPIO MUX pinout 30
- USB Power 35
- Controller 35
- CLSTN[0] 36
- MLSTN[0] 36
- CUSTN[0] 37
- RED[0] 38
- GREEN[0], BLUE[0] 38
- C interface 39
- USB Interface 39
- Reserved pins 41
- Address and register maps 42
- BBus peripheral address map 43
- Electrical characteristics 44
- Maximum power dissipation 45
- Typical power dissipation 45
- DC electrical characteristics 46
- USB DC electrical outputs 47
- 44 48
- Power sequencing 49
- Memory timing 50
- SDRAM burst read (16-bit) 51
- SDRAM burst write (16-bit) 52
- SDRAM burst read (32-bit) 52
- SDRAM burst write (32-bit) 53
- SDRAM load mode 54
- SDRAM refresh mode 54
- Clock enable timing 54
- SRAM timing 55
- 52 56
- WTWR = from 0 to 15 60
- 57 61
- 58 62
- Ethernet timing 63
- Ethernet MII timing 64
- Ethernet RMII timing 64
- PCI timing 65
- Internal PCI arbiter timing 66
- 64 68
- C timing 69
- LCD timing 70
- 68 72
- LCD output timing 73
- SPI timing 74
- 72 76
- IEEE 1284 timing 77
- USB timing 78
- USB full speed load 79
- USB low speed load 79
- 80
- JTAG timing 81
- Clock timing 82
- 79 83
- Packaging 84
- NS9750B-A1, 388 BGA 86
- Product specifications 87
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