Digi NS9750 Uživatelský manuál stáhnout pdf (Strana 14)

System Clock

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NS9750B-A1 Datasheet 03/2006

Figure 2: NS9750B-A1 system clock

The PLL parameters are initialized on powerup reset and can be changed by software from f

max

1/2 f

max

. For a 200 MHz grade, then, the CPU may change from 200 MHz to 100 MHz, the AHB

system bus may change from 100 MHz to 50 MHz, and the peripheral BBus may change from 50 MHz

to 25 MHz. If changed by software, the system resets automatically after the PLL stabilizes

(approximately 4 ms).

The system clock provides clocks for CPU, AHB system bus, peripheral BBus, PCI/CardBus, LCD,

timers, memory controller, and BBus modules (serial modules and 1284 parallel port).

The Ethernet MAC uses external clocks from a MII PHY or a RMII PHY. For a MII PHY, these clocks are

input signals:

rx_clk on pin T3 for receive clock and tx_clk on pin V3 for transmit clock. For a RMII,

there is only one clock, and it connects to the

rx_clk on pin T3. In this case, the transmit clock

tx_clk, pin V3, should be tied low.

PCI/CardBus, LCD controller, serial modules (UART, SPI), and 1284 port can optionally use external

clock signals.

SM_Oscillator

1 3

VCC

GND

TEST OUT

SN74LVC1GU04

2 4

NS9750B-A1

Y2_OUT

TB2

X1_SYS

3R3V

R12

C20

10pF

X2_XTAL

Y2_PWR

330 OHM

C19

10pF

100nF

X1_SYS_OSC

(20-40MHz)

330 OHM

The clock input range is 20-40MHz. A

29.4912 MHz oscillator allows full speed

operation.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 87 88

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