Digi NS9750 Uživatelský manuál stáhnout pdf (Strana 20)

System Memory interface signals

16       

NS9750B-A1 Datasheet 03/2006

System Memory interface signals

Table 6 describes the System Memory interface signals in more detail. All signals are internal to the

chip.

Name I/O Description

addr[27:0] O Address output. Used for both static and SDRAM devices. SDRAM

memories use bits [14:0]; static memories use bits [25:0].

clk_en[3:0] O SDRAM clock enable. Used for SDRAM devices.

Note:

The clk_en signals are associated with the dy_cs_n signals.

clk_out[3:1] O SDRAM clocks. Used for SDRAM devices.

clk_out[0] O SDRAM clk_out[0] is connected to clk_in.

data[31:0] I/O Data to/from memory. Used for the static memory controller and the

dynamic memory controller.

data_mask[3:0] O Data mask output to SDRAMs. Used for SDRAM devices.

clk_in I Feedback clock. Always connects to clk_out[0].

byte_lane_sel_n[3:0] O Static memory byte lane select, active low, or write_enable_n for byte-

wide devices.

cas_n O Column address strobe. Used for SDRAM devices.

dy_cs_n[3:0] O SDRAM chip selects. Used for SDRAM devices.

st_oe_n O Output enable for static memories. Used for static memory devices.

ras_n O Row address strobe. Used for SDRAM devices.

st_cs_n[3:0] O Static memory chip selects. Default active low. Used for static memory

devices.

we_n O Write enable. Used for SDRAM and static memories.

ta_strb I Slow peripheral transfer acknowledge can be used to terminate static

memory cycles sooner than the number of wait states programmed in the

chip select setup register.

Table 6: System Memory interface signal descriptions

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 87 88

Žádné komentáře

Digi NS9750 Uživatelský manuál Strana 20