Digi NS9750 Uživatelský manuál stáhnout pdf (Strana 6)

NS9750B-A1 Features

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NS9750B-A1 Datasheet 03/2006

Flexible LCD controller

 Supports most commercially available

displays:

– Active Matrix color TFT displays — Up

to 24bpp direct 8:8:8 RGB; 16M colors

– Single and dual panel color STN

displays — Up to 16bpp 4:4:4 RGB;

3375 colors

– Single and dual-panel monochrome

STN displays — 1, 2, 4bpp palettized

gray scale

 Formats image data and generates timing

control signals

 Internal programmable palette LUT and

grayscaler support different color

techniques

 Programmable panel-clock frequency

USB ports

 USB v.2.0 full speed (12 Mbps) and low

speed (1.5 Mbps)

 Configurable to device or OHCI host

– USB host is bus master

– USB device supports one bidirectional

control endpoint and 11

unidirectional endpoints

 All endpoints supported by a dedicated

DMA channel; 13 channels total

 20 byte RX FIFO and 20 byte TX FIFO

Serial ports

 4 serial modules, each independently

configurable to UART mode, SPI master

mode, or SPI slave mode

 Bit rates from 75 bps to 921.6 kbps:

asynchronous x16 mode

 Bit rates from 1.2 kbps to 6.25 Mbps:

synchronous mode

 UART provides:

– High-performance hardware and

software flow control

– Odd, even, or no parity

– 5, 6, 7, or 8 bits

– 1 or 2 stop bits

– Receive-side character and buffer gap

timers

 Internal or external clock support, digital

PLL for RX clock extraction

 4 receive-side data match detectors

 2 dedicated DMA channels per module, 8

channels total

 32 byte TX FIFO and 32 byte RX FIFO per

module

I

2

C port

 I

2

C v.1.0, configurable to master or slave

mode

 Bit rates: fast (400 kHz) or normal (100

kHz) with clock stretching

 7-bit and 10-bit address modes

 Supports I

2

C bus arbitration

1284 parallel peripheral port

 All standard modes: ECP, byte, nibble,

compatibility (also known as SPP or

“Centronix”)

 RLE (run length encoding) decoding of

compressed data in ECP mode

 Operating clock from 100 kHz to 2 MHz

 Two dedicated DMA channels

High performance multiple-master/distributed

DMA system

 Intelligent bus bandwidth allocation

(patent pending)

 System bus and peripheral bus

System bus:

 Every system bus peripheral is a bus

master with a dedicated DMA engine

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